Is it a modern CPU? Not at all. But you might find it is just the right level of wax on and wax off, to get you started. There is bad news and good news. The bad news is the book is years out of print.
The good news is that the book was so popular as a college text that it is easy to find gently used copies in the usual places hint: Amazon. There are probably minor differences in Blue depending on the version. A bit word memory serves as a unified data and instruction storage with a maximum of 4K words most of its commercial counterparts could handle 32K. There are a handful of instructions well, if 16 is a handful; see right , which each use two major cycles: fetch and execute.
Those major cycles divide up into eight clock phases each. This is why this type of CPU is a reasonable place to start on your way to designing the next great supercomputer. Avoiding things like pipelines and multiple instruction issue let you focus on the core principles. These principles are at the heart of every CPU, even those that have many other details obscuring their fundamental operation.
All of these things connect to a common internal bus. Some things can only drive the bus like the output of the ALU. Some things only read from the bus like the memory address register. Some things, like the accumulator or memory buffer register, do both. The control unit orchestrates all these resources by enabling one device to write to the internal bus and at least one device to read from the bus in a given cycle. The internals are very simple, especially compared to a modern CPU.
The outputs include things like the sum of Y and Z, the inverse of Z, and so on. This is unnecessary for modern memory systems. Fetch 1 is a good example of where the control unit does two writes in a single subcycle since the program counter has to go to the memory address register and Z. For simple instructions, execution can occur in Fetch 7 and 8.
For example, a NOT instruction inverts the accumulator, so Fetch 6 for that instruction could put the accumulator on the internal bus and load Z. Then the final Fetch subcycle can move the ALU output to the accumulator. Also, it would have to flag the control unit to start a new Fetch cycle instead of an Execute cycle. So doing nothing, in the case of the NOT instruction, is sufficient to meet the requirement that the next cycle is a Fetch. Some instructions need more work, however. This provides 8 more subcycles for the control unit to manipulate resources in response to the instruction.
With modern high-speed memory, you might be able to condense everything into the 8 phases of Fetch, but remember Blue had relatively slow memory that needed a refresh after a read.
How does the control unit know what to do? Each instruction has a 4-bit opcode bits , and the remaining bits specify an address now you see why Blue can only handle 4K words of memory. Once the instruction is in the instruction register, decoding the top 4 bits determines what happens in the next cycles. The concepts are the same however you do it.
Then you can create logic to do each of the actions required. All of these that are the same get merged with an OR gate and fed to the register or other resource to make it do what it is supposed to do. The resources are simple. You load the bus into a register, or you gate the register out to the bus. Consider phase 4 of a Fetch cycle. It is supposed to have the ALU gate the sum output to the bus and then also have the PC read from the bus this is how the CPU sets the next fetch address.
One input is the F bit indicating a Fetch cycle , and the other is CP4 meaning the 4th subcycle. Presumably, other things will want to gate the sum output the ADD instruction or load the PC a JMP instruction so those outputs will really go to an OR gate that connects to the resource in question see figure, below. The same output will drive the accumulator to read from the bus again, through an OR gate that merges all the things that signal an accumulator load.
When you look at it this way, the CPU is simple. Just a bunch of readers and writers on a bus and a state machine that enables different items at different times. I already mentioned the core memory features of Blue are hardly necessary today. In particular, you could read or write memory on each phase, if you wanted to. You could make the PC know how to increment itself so that the operation could share a slot with something that used the internal bus.
A capable graphic design tool not only enhances efficiency, but it also helps in putting stunning creativity into real-world design.
Disclaimer: Please note, I may receive affiliate compensation for some of the links below at no cost to you if you choose to purchase one of the products. However, these are my top picks for graphic design that I have used and tested this year.
You can read my affiliate disclosure in my privacy policy. Adobe Photoshop is synonymous with photo editing for graphic designers. It is one of the most popular photo editing software tools in the market in a robust package that offers excellent graphic design capabilities. Get started with Adobe Photoshop today.
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This chip is only a minimal upgrade from the previous generation iH, so only jump on the newer chip if you have to upgrade from an older laptop. Also note: Intel i7 H is a laptop-only processor, and isn't sold individually.
Included in this guide: 1. AMD Ryzen 9 x. Specifications Base Clock: 3. Boost Clock: 4. Threads: L3 Cache: 64MB.
Reasons to avoid - Single Core performance just okay - Expensive. Intel iK. Boost Clock: : 5GHz. Threads: : L3 Cache: : 16MB. Reasons to avoid - Expensive - Minor improvements over previous generation.
AMD Ryzen 9 X. Specifications Base clock: 3. Boost clock: 4. L3 cache: 64MB. Reasons to avoid - Fewer PCle lanes - No quad-channel memory. Intel Core iXE. Specifications Base clock: 3GHz. L3 cache: AMD Ryzen 5
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